1. Field of the Invention
The present disclosure relates to liquid display technology, and more particularly to a display device having the array substrate.
2. Discussion of the Related Art
Thin-film transistor (TFT) is a key component of flat display device, which may be formed on the glass substrate or a plastic substrate. Usually, the TFT may operate as a lighting device and a driving device incorporated with LCD or OLED. The Thin-film Transistor Liquid Crystal Display (TFT-LCD) is characterized by attributes such as small dimension, low power consumption, and no radiations, and thus has been the main trend in the flat display market.
The array substrate of the TFT-LCD may be formed by structure patterns formed by a plurality of masking processes. Each of the masking process includes coating, exposure, development, etching and peeling, respectively, wherein the etching process may include dry etching and wet etching. The number of masking steps may be adopted to evaluate the complexity of the manufacturing process of the array substrate. That is, the manufacturing cost may be reduced by decreasing the number of manufacturing steps. The number of the steps within the manufacturing process of TFT array substrates evolves from 7Mask to 5Mask. Currently, 5Mask solution has become the mainstream of the manufacturing process of the TFT-LCD array substrates. 5Mask solution includes 5 mask processes, including gate electrode mask, Active layer mask, S/D mask, Via mask, and a pixel electrode mask (Pixel Mask).
At present, in order to further reduce manufacturing cost, some manufacturers begin to use 4Mask solution, which bases on the 5Mask solution plus the GrayToneMask process, Active Mask process and S/D Mask process, so as to form a Mask. By adjusting the etching process (Etch), the original Active Mask and S/D Mask function may be completed, that is, the technical effect of Mask process may be completed through a Mask process.
Referring to FIG. 1a-1g, with respect to the 4Mask process, the second masking process is adopted to form the active layer, the source electrode, and the drain electrode. The second masking process includes the following steps:
(1) As shown in FIG. 1a, a semiconductor thin-film layer 2, a N+ doping thin-film layer 3, a metal thin-film layer 4, and a photo-resistor layer 5 are formed on an gate insulation layer 1 in sequence.
(2) As shown in FIG. 1b, the GrayToneMask process is applied to the photo-resistor layer 5 to obtain a first photo-resistor masking 5a. 
(3) As shown in FIG. 1c, under the protection of the first photo-resistor masking 5a, a first wet etching process is adopted to etch the metal thin-film layer 4.
(4) As shown in FIG. 1d, under the protection of the first photo-resistor masking 5a, the first dry etching process is adopted to etch the semiconductor thin-film layer 2 and the N+ doping thin-film layer 3 to obtain an active layer 2a. 
(5) As shown in FIG. 1e, applying a plasma ashing process to the first photo-resistor masking 5a to obtain a second photo-resistor mask 5b such that a metal thin-film layer 4 is exposed from a middle area of the second photo-resistor mask 5b. 
(6) As shown in FIG. 1f, under the protection of the second photo-resistor mask 5b, a second wet etching process is adopted to etch the metal thin-film layer 4 to obtain a source electrode 4a and a drain electrode 4b. 
(7) As shown in FIG. 1g, under the protection of the second photo-resistor mask 5b, a second wet etching process is adopted to etch the N+ doping thin-film layer 3 to form the N+ contact layer 3a, 3b. 
(8) As shown in FIG. 1h, the second photo-resistor mask 5b is removed.
In step (6), when the etching process is applied, due to the isotropic attribute, the lateral sides of the metal thin-film layer 4 are seriously etched such that edges of the source electrode 4a and the drain electrode 4b shrinkage when compared to the edge of the second photo-resistor mask 5b. As shown in FIG. 1f, in step (7), due to the anisotropy attribute of the dry etching process, the etched plasma crash vertically, the edges of the formed N+ contact layer 3a, 3b align with the edge of the second photo-resistor mask 5b, as shown in FIG. 1g. That is, as shown in FIG. 1h, the edges of the source electrode 4a and the drain electrode 4b do not smoothly transit into the corresponding edges of the N+ contact layer 3a, 3b. Instead, edges of the N+ contact layer 3a, 3b includes a protrusive tail 6 when being compared with the edges of the source electrode 4a and the drain electrode 4b. This may affect the length of the trench of the TFT, and may not be beneficial for the performance of the TFTs.